1. Field of the Invention
This invention relates to pulse-width modulation (PWM) amplifiers used for power amplification of audio signals, wherein clipping is suppressed so as to avoid deterioration of waveforms.
This application claims priority on Japanese Patent Applications Nos. 2004-197347 and 2004-197385, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Conventionally, pulse-width modulation (PWM) effected on large-amplitude signals may cause clipping, which in turn causes partial loss of waveforms (e.g., flattening or partial distortion of waveforms) reproduced based on pulse-width modulated signals. Japanese Examined Utility Model Publication No. H04-38566 teaches a technology for the prevention of partial loss of waveforms due to clipping occurring in pulse-width modulation, wherein clipping is canceled by compulsorily introducing pulses upon the detection of a clipped state.
FIG. 4 is a block diagram showing a conventionally known class-D amplifier using pulse-width modulation, wherein an input terminal 301 receives an analog input signal. A PWM circuit 302 converts the analog input signal into a pulse-width. modulated signal (or a PWM signal), which is then supplied to a drive circuit 304 via an OR circuit 303. The drive circuit 304 outputs a control signal to a switch SW1 via a capacitor C301 for blocking dc components. The PWM signal is also delivered to a drive circuit 306 via an AND circuit 305. The drive circuit 306 outputs a control signal to a switch SW2 via a capacitor C302 for blocking dc components. In accordance with switching operations of the switches SW1 and SW2, the PWM signal is subjected to switched amplification, so that an amplified PWM signal is supplied to a pulse-analog decoding circuit 308, where it is decoded into an analog output signal, which is then output to an output terminal 309.
A pulse interval detection circuit 310 normally monitors the PWM signal input into the pulse-analog decoding circuit 308. An output signal of the pulse interval detection circuit 310 is supplied to a second input terminal of the AND circuit 305 and is also supplied to a second input terminal of the OR circuit 303 via an inverter 307.
When clipping does not occur in the PWM signal, the output signal of the pulse interval detection circuit 310 remains at a high level, so that the OR circuit 303 and the AND circuit 305 directly transmit the PWM signal to the drive circuits 304 and 306 respectively.
When clipping occurs in the PWM signal so that its level may be maintained at a high level or a low level for a while, the pulse interval detection circuit 310 switches over the output signal thereof from the high level to the low level at a prescribed timing, at which both of the outputs of the OR circuit 303 and AND circuit 305 are inverted. Thus, a pulse (or pulses) is compulsorily introduced into the PWM signal to be supplied to the switches SW1 and SW2. This creates ac components in the input signals of the switches SW1 and SW2, whereby switched amplification can be maintained.
Japanese Patent No. 3130919 teaches a technology for the prevention of clipping in which an analog input signal having large amplitude is reduced to half in level. In this technology, an instantaneous voltage of an analog input signal is detected by a voltage level detection circuit so that when it matches source voltage, a pulse-width modulation (PWM) amplifier is switched over into an anti-clipping mode from a normal mode, whereby the gain of a pre-amplification circuit, which is arranged prior to the PWM amplifier, is reduced to half while voltage applied to a switched amplification stage is doubled; thus, it is possible to avoid the occurrence of clipping.
Clipping may depend upon the level of the analog input signal; that is, the level of the analog input signal may not be so high that the clipped state of a waveform may become discontinuous, or the clipped state occurs sporadically, which is shown in FIGS. 5C and 5D. When a secondary integration component is introduced into the circuitry in order to improve noise characteristics with respect to the analog input signal, there may occur a phenomenon in which clipped states occur per every other pulse in a stable manner, which is shown in FIGS. 5A and 5B.
In the technology disclosed in Japanese Patent No. 3130919, the circuit operation may be interrupted or become unstable when it is switched over into the anti-clipping mode or returned to the normal mode. This causes distortion of an output waveform. In the anti-clipping mode, the analog input signal is processed with half of the ‘normal’ source voltage, which may deteriorate noise characteristics. In particular, these problems may apparently occur when ‘relatively small’ clipping occurs in waveforms.
In addition, the aforementioned technology requires a specially-designed power source circuit, which can produce double voltage that is double the normal voltage produced by the normal power source circuit, which may increase the overall scale of the power source system. Such a power source circuit providing double voltage is used only in the anti-clipping mode, which certainly reduces the overall power use efficiency.
In the technology disclosed in Japanese Examined Utility Model Publication No. H04-38566, pulses are compulsorily introduced into PWM signals, which may cause disturbance in a closed loop realizing feedback from the latter stage to the former stage with respect to the PWM circuit. Such disturbance causes distortion of an output waveform, which apparently appears in the case of relatively small clipping.
When an analog input signal has an excessive amplitude so that positive voltage (or negative voltage) is continuously applied to the circuitry, the capacitor C301 or C302 must be excessively charged, and this causes trouble in the decoding operation. It is necessary to avoid the occurrence of this situation.
When pulses are simultaneously introduced into the drive circuits 304 and 306 due to error operation, which may occur due to noise, a relatively large current may be forced to flow instantaneously between a positive voltage +VPX and a negative voltage −VMX, so that the power source circuit (not shown) and the switches SW1 and SW2 may likely be destroyed. It is necessary to avoid the occurrence of this situation.